IMPLEMENTACIÓN DE UNA MAQUINA DE VECTORES SOPORTE EMPLEANDO FPGA


Authors

  • JORGE E. HERNANDEZ L.
  • SANTIAGO SALAZAR G.

Abstract

En este artículo, se presenta el diseño y la implementación de una maquina de vector de soporte (SVM) sobre un dispositivo lógico programable (PLD). La maquina es utilizada para solucionar el problema de la XOR. Además, se presenta la implementación del estándar IEEE 754 para la representación de números en punto flotante. La arquitectura del sistema implementado es descrito en detalle y sintetizada sobre una tarjeta del sistema de desarrollo con un arreglo de compuerta programable por campo - FPGA (ALTERA® FLEX10K).

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Published

2006-08-17

How to Cite

HERNANDEZ L., J. . E. ., & SALAZAR G., S. . (2006). IMPLEMENTACIÓN DE UNA MAQUINA DE VECTORES SOPORTE EMPLEANDO FPGA. Scientia Et Technica, 2(31). Retrieved from https://ojs2.utp.edu.co/index.php/revistaciencia/article/view/6383

Issue

Vol. 2 No. 31 (2006)

Section

Eléctrica

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Copyright (c) 2017 Scientia et technica

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